LLP in Chain Inverter by using CMOS Circuit

This paper provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, we focus on leakage power reduction. Although leakage power was negligible at 0.18μ technology and in nano scale technology, such as 0.07μ, leakage power is almost equal to dynamic power consumption. This paper presents heretofore unexplored methods for low-power VLSI design. In particular, the Low Leakage approach provides what may be the best solution for VLSI designers concerned about the twin problems of low static power and maintenance of VLSI logic state during sleep mode. For such a two-headed problem, the Low Leakage approach can provide two orders of magnitude (100X) or more static power reduction over the best prior approach; however, there is a cost potentially quite small – in terms of delay increase and area overhead. In short, Low Leakage principles provide heretofore unknown Pareto points for consideration in VLSI design.